The storage capacity of a memory chip is dependent on the number of memory cells in the chip. High density dynamic random access memory (DRAMs) cells are comprised of two main components, a field-effect transistor (FET) and a storage capacitor. In DRAM fabrication, there is a continuing need to provide higher density memories in order to further increase data storage capacity.
Increasing circuit density in DRAM fabrication requires a reduction in the size of the FETs and storage capacitors of memory cells. As a solution to this problem, trench capacitors, vertically stacked capacitors, elevated source and drain structures, and other improved structures have been developed which require less surface area. However, photolithographic processing limits the minimal size of the feature and the resulting device that can be formed. Thus, the density of storage cells of a memory array has been limited by the resolution capability of the available photolithographic equipment.
Therefore, there is a need for a semiconductor fabrication technique to provide high density memory structures that can be fabricated without the limitations of photolithographic processing steps.